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| 1 ltc3727lx-1 3727lx1fa high efficiency, 2-phase synchronous step-down switching regulator figure 1. high efficiency dual 12v/5v step-down converter wide output voltage range: 0.8v v out 14v out-of-phase controllers reduce required inputcapacitance and power supply induced noise opti-loop compensation minimizes c out 1.5% output voltage accuracy power good output voltage monitor phase-lockable fixed frequency 250khz to 550khz dual n-channel mosfet synchronous drive wide v in range: 4v to 32v operation very low dropout operation: 99% duty cycle adjustable soft-start current ramping foldback output current limiting output overvoltage protection low shutdown i q : 20 a selectable constant-frequency or burst mode operation small 28-lead ssop and 5mm 5mm qfn packages the ltc 3727lx-1 is a high performance dual step-down switching regulator controller that drives all n-channelsynchronous power mosfet stages. a constant-frequency current mode architecture allows phase-lockable frequency of up to 550khz. power loss and noise due to the esr of the input capacitors are minimized by operating the two controller output stages out of phase. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. there is a precision 0.8v reference and a power good output indicator. a wide 4v to 28v (32v maximum) input supply range encompasses all battery chemistries. table 1 part v in v ref accuracy latch- minimum number range overtemperature off on-time ltc3727lx-1 4v to 32v 1.5% no 120ns ltc3727 4v to 36v 1% yes 180ns ltc3727-1 4v to 36v 1% no 180ns ltc3727a-1 4v to 36v 1% no 120ns telecom systems automotive systems distributed dc power systems + 4.7 f m2 m1 0.1 f 105k 1% 1000pf 8 h 220pf 1 f ceramic 22 f 50vceramic + 47 f 6vsp 0.015 ? 20k1% 15k v out1 5v5a m4 m3 0.1 f 280k 1% 15 h 220pf 1000pf + 56 f 15vsp 0.015 ? 20k1% 15k v out2 12v4a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd sense1 + sense2 + sense1 sense2 v osense1 v osense2 i th1 i th2 v in pgood intv cc run/ss1 run/ss2 v in 18v to 28v m1, m2, m3, m4: fds6680a 3727lx1 f01 0.1 f 0.1 f ltc3727lx-1 pllin descriptio u features applicatio s u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919. downloaded from: http:///
2 ltc3727lx-1 3727lx1fa order part number ltc3727lxeg-1 input supply voltage (v in ).........................32v to 0.3v top side driver voltages (boost1, boost2) ...................................40v to 0.3v switch voltage (sw1, sw2) .........................32v to 5v intv cc, extv cc , (boost1-sw1), (boost2-sw2) ........................................8.5v to 0.3v run/ss1, run/ss2, pgood ..................... 7v to 0.3v sense1 + , sense2 + , sense1 , sense2 voltages .....................................14v to 0.3v pllin, pllfltr, fcb voltages ........... intv cc to 0.3v t jmax = 125 c, ja = 95 c/w absolute axi u rati gs w ww u package/order i for atio uu w 12 3 4 5 6 7 8 9 1011 12 13 14 top view g package 28-lead plastic ssop 2827 26 25 24 23 22 21 20 19 18 17 16 15 run/ss1 sense1 + sense1 v osense1 pllfltr pllin fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + pgoodtg1 sw1 boost1 v in bg1extv cc intv cc pgndbg2 boost2 sw2 tg2 run/ss2 consult ltc marketing for parts specified with wider operating temperature ranges. (note 1) i th1, i th2 , v osense1 , v osense2 voltages ... 2.7v to 0.3v peak output current < 10 s (tg1, tg2, bg1, bg2) .... 3a intv cc peak output current ................................ 50ma operating temperature range (note 2) ..... 40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ................. 65 c to 125 c lead temperature (soldering, 10 sec, g package)............................. 300 c solder reflow temperature (uh package) ........... 265 c 32 31 30 29 28 27 26 25 9 10 11 12 13 top view 33 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v osense1 pllfltr pllin fcb i th1 sgnd 3.3v out i th2 boost1v in bg1extv cc intv cc pgndbg2 boost2 ncsense1 sense1 + ncrun/ss1 pgood tg1 sw1 v osense2 nc sense2 sense2 + run/ss2 tg2 sw2 nc uh package 32-lead (5mm 5mm) plastic qfn order part number ltc3727lxeuh-1 t jmax = 125 c, ja = 34 c/w exposed pad (pin 33) is sgnd (must be soldered to pcb) uh part marking 727lx1 the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. electrical characteristics order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ symbol parameter conditions min typ max units main control loops v osense1, 2 regulated feedback voltage (note 4); i th1, 2 voltage = 1.2v 0.788 0.800 0.812 v i vosense1, 2 feedback current (note 4) 5 50 na v reflnreg reference voltage line regulation v in = 3.6v to 30v (note 4) 0.002 0.02 %/v downloaded from: http:/// 3 ltc3727lx-1 3727lx1fa symbol parameter conditions min typ max units v loadreg output voltage load regulation (note 4) measured in servo loop; ? i th voltage = 1.2v to 0.7v 0.1 0.5 % measured in servo loop; ? i th voltage = 1.2v to 2.0v 0.1 0.5 % g m1, 2 transconductance amplifier g m i th1, 2 = 1.2v; sink/source 5 a (note 4) 1.3 mmho g mgbw1, 2 transconductance amplifier gbw i th1, 2 = 1.2v (note 4) 3 mhz i q input dc supply current (note 5) normal mode v in = 15v, extv cc tied to v out1 , v out1 = 8.5v 1 ma shutdown v run/ss1, 2 = 0v 20 35 a v fcb forced continuous threshold 0.76 0.800 0.84 v i fcb forced continuous pin current v fcb = 0.85v 0.30 0.18 0.05 a v binhibit burst inhibit (constant-frequency) measured at fcb pin 6.8 7.3 v threshold uvlo undervoltage lockout v in ramping down 3.5 4 v v ovl feedback overvoltage lockout measured at v osense1, 2 0.84 0.86 0.88 v i sense sense pins total source current (each channel) v sense1 , 2 = v sense1 + , 2 + = 0v 85 60 a df max maximum duty factor in dropout 98 99.4 % i run/ss1, 2 soft-start charge current v run/ss1, 2 = 1.9v 0.5 1.2 a v run/ss1, 2 on run/ss pin on threshold v run/ss1, v run/ss2 rising 1.0 1.5 1.9 v v sense(max) maximum current sense threshold v osense1, 2 = 0.7v,v sense1 , 2 = 12v 105 135 165 mv tg transition time: (note 6) tg1, 2 t r rise time c load = 3300pf 50 90 ns tg1, 2 t f fall time c load = 3300pf 50 90 ns bg transition time: (note 6) bg1, 2 t r rise time c load = 3300pf 40 90 ns bg1, 2 t f fall time c load = 3300pf 40 80 ns tg/bg t 1d top gate off to bottom gate on delay c load = 3300pf each driver 90 ns synchronous switch-on delay time bg/tg t 2d bottom gate off to top gate on delay c load = 3300pf each driver 90 ns top switch-on delay time t on(min) minimum on-time 120 ns intv cc linear regulator v intvcc internal v cc voltage 8.5v < v in < 30v, v extvcc = 6v 7.2 7.5 7.8 v v ldo int intv cc load regulation i cc = 0ma to 20ma, v extvcc = 6v 0.2 1.0 % v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 8.5v 70 160 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive 6.9 7.3 v v ldohys extv cc hysteresis 0.3 v oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 350 380 430 khz f low lowest frequency v pllfltr = 0v 220 255 290 khz f high highest frequency v pllfltr 2.4v 460 530 580 khz r pllin pllin input resistance 100 k ? i pllfltr phase detector output current sinking capability f pllin < f osc ?5 a sourcing capability f pllin > f osc 15 a the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. electrical characteristics downloaded from: http:/// 4 ltc3727lx-1 3727lx1fa 3.3v linear regulator v 3.3out 3.3v regulator output voltage no load 3.25 3.35 3.45 v v 3.3il 3.3v regulator load regulation i 3.3 = 0ma to 10ma 0.5 2.5 % v 3.3vl 3.3v regulator line regulation 6v < v in < 30v 0.05 0.3 % pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level, either controller v osense with respect to set output voltage v osense ramping negative 6 7.5 9.5 % v osense ramping positive 6 7.5 9.5 % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolutemaximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3727lx-1 is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the ?0 c to 85 c operating temperature range are assured by design, characterization andcorrelation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3727lxeg-1: t j = t a + (p d ?95 c/w) ltc3727lxeuh-1: t j = t a + (p d ?34 c/w) efficiency vs output current and mode (figure 13) efficiency vs output current(figure 13) efficiency vs input voltage(figure 13) typical perfor a ce characteristics uw output current (a) 0.001 0 efficiency (%) 10 30 40 50 100 70 0.01 0.1 1 3727lx1 g01 20 80 90 60 10 forcedcontinuous mode burst mode operation v in = 15v v out = 8.5v constant-frequency (burst disable) output current (a) 0.001 efficiency (%) 70 80 10 3727lx1 g02 6050 0.01 0.1 1 100 90 v in = 10v v in = 15v v in = 7v v in = 20v v out = 5v input voltage (v) 5 efficiency (%) 70 80 3727lx1 g03 60 50 15 25 32 100 v out = 5v i out = 3a 90 the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units note 4: the ltc3727lx-1 is tested in a feedback loop that servos v ith1, 2 to a specified voltage and measures the resultant v osense1, 2. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information.note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. downloaded from: http:/// 5 ltc3727lx-1 3727lx1fa maximum current sense thresholdvs duty factor maximum current sense thresholdvs percent of nominal output voltage (foldback) maximum current sense thresholdvs v run/ss (soft-start) current sense thresholdvs i th voltage load regulation v ith vs v run/ss typical perfor a ce characteristics uw duty factor (%) 0 0 v sense (mv) 25 50 75 100 125 150 20 40 60 80 3727lx1 g07 100 percent of nominal output voltage (%) 0 v sense (mv) 90 120 150 80 3727lx1 g08 60 30 75 105 135 45 15 0 20 40 60 100 v run/ss (v) 0 50 v sense (mv) 75 100 125 150 1234 3727lx1 g09 56 v sense(cm) = 1.6v v ith (v) 0 v sense (mv) 25 50 75 1.5 2.5 3727lx1 g10 0 ?5 ?0 0.5 1.0 2.0 100 125 150 load current (a) 0 normalized v out (%) 0.2 0.1 4 3727lx1 g11 0.3 0.4 1 2 3 5 0.0 fcb = 0vv in = 15v figure 1 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 3727lx1 g12 56 v osense = 0.7v supply current vs input voltage and mode (figure 13) extv cc voltage drop input voltage (v) 0 0 supply current ( a) 400 1000 10 20 3727lx1 g04 200 800 600 30 32 bothcontrollers on shutdown current (ma) 0 extv cc voltage drop (mv) 60 80 100 30 50 3727lx1 g05 40 20 0 10 20 40 120 140 160 v extvcc = 8.5v internal 7.5v ldo line regulation input voltage (v) 0 6.8 intv cc voltage (v) 6.9 7.1 7.2 7.3 20 7.7 3727lx1 g06 7.0 10 5 25 30 15 32 7.4 7.5 7.6 i load = 1ma downloaded from: http:/// 6 ltc3727lx-1 3727lx1fa soft-start up (figure 12) i l 5a/div v out 5v/div v run/ss 5v/div v in = 20v 50ms/div 3727lx1 g16 v out = 12v load step (figure 12) v out 200mv/div i l 2a/div v in = 15v 50 s/div 3727lx1 g17 v out = 12v load step = 0a to 3aburst mode operation load step (figure 12) v out 200mv/div i l 2a/div v in = 15v 50 s/div 3727lx1 g18 v out = 12v load step = 0a to 3acontinuous mode input source/capacitorinstantaneous current (figure 12) v sw1 20v/div v in = 15v 1 s/div 3727lx1 g19 v out1 = 12v v out2 = 5v i out1 = i out2 = 2a burst mode operation (figure 12) v out 20mv/div i l 0.5a/div v in = 15v 50 s/div 3727lx1 g20 v out = 12v v fcb = open i out = 20ma constant frequency (burst inhibit)operation (figure 12) v out 20mv/div i l 0.5a/div v in = 15v 5 s/div 3727lx1 g21 v out = 12v v fcb = 7.5v i out = 20ma v sw2 20v/div typical perfor a ce characteristics uw i in 1a/div sense pins total source current v sense common mode voltage (v) 0 400 i sense ( a) 300 250 200 ?50 ?00 ?0 5 10 3727lx1 g13 0 50 100 350 15 dropout voltage vs output current(figure 13) run/ss current vs temperature output current (a) 0 1.0 1.2 1.4 4 3727lx1 g14 0.80.6 123 5 0.4 0.2 0 dropout voltage (v) v out = 5v r sense = 0.015 ? r sense = 0.010 ? temperature ( c) ?0 ?5 0 run/ss current ( a) 0.2 0.6 0.8 1.0 75 100 50 1.8 3727lx1 g15 0.4 0 25 125 1.2 1.4 1.6 downloaded from: http:/// 7 ltc3727lx-1 3727lx1fa undervoltage lockoutvs temperature typical perfor a ce characteristics uw temperature ( c) ?0 undervoltage lockout (v) 3.40 3.45 3.50 25 75 3727lx1 g25 3.35 3.30 ?5 0 50 100 125 3.25 3.20 current sense pin input currentvs temperature extv cc switch resistance vs temperature oscillator frequencyvs temperature temperature ( c) ?0 25 25 current sense input current ( a) 29 35 0 50 75 3727lx1 g22 27 33 31 25 100 125 v out = 5v temperature ( c) ?0 25 0 extv cc switch resistance ( ? ) 4 10 0 50 75 3727lx1 g23 2 8 6 25 100 125 temperature ( c) ?0 400 500 700 25 75 3727lx1 g24 300200 ?5 0 50 100 125 100 0 600 frequency (khz) v pllfltr = 5v v pllfltr = 1.2v v pllfltr = 0v downloaded from: http:/// 8 ltc3727lx-1 3727lx1fa run/ss1, run/ss2 (pins 1, 15/pins 28, 13): combina- tion of soft-start and run control inputs. a capacitor toground at each of these pins sets the ramp time to full output current. forcing either of these pins back below 1.0v causes the ic to shut down the circuitry required for that particular controller. sense1 + , sense2 + (pins 2, 14/pins 30, 12): the (+) input to the differential current comparators. the i th pin voltage and controlled offsets between the sense and sense + pins in conjunction with r sense set the current trip threshold.sense1 , sense2 (pins 3, 13/pins 31, 11): the (? input to the differential current comparators.v osense1 , v osense2 (pins 4, 12/pins 1, 9): receives the remotely-sensed feedback voltage for each controller froman external resistive divider across the output. pllfltr (pin 5/pin 2): the phase-locked loop? lowpass filter is tied to this pin. alternatively, this pin can be drivenwith an ac or dc voltage source to vary the frequency of the internal oscillator. pllin (pin 6/pin 3): external synchronization input to phase detector. this pin is internally terminated to sgndwith 50k ? . the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with therising edge of the pllin signal. fcb (pin 7/pin 4): forced continuous control input. this input acts on both controllers and is normally used toregulate a secondary winding. pulling this pin below 0.8v will force continuous synchronous operation. do not leave this pin floating. i th1, i th2 (pins 8, 11/pins 5, 8): error amplifier outputs and switching regulator compensation points. each as-sociated channels?current comparator trip point increases with this control voltage. sgnd (pin 9/pin 6): small signal ground. common to both controllers; must be routed separately fromhigh current grounds to the common (? terminals of the c out capacitors. 3.3v out (pin 10/pin 7): linear regulator output. capable of supplying 10ma dc with peak currents as high as 50ma. uu u pi fu ctio s pgnd (pin 20/pin 19): driver power ground. connects to the sources of bottom (synchronous) n-channel mos-fets, anodes of the schottky rectifiers and the (? terminal(s) of c in . intv cc (pin 21/pin 20): output of the internal 7.5v linear low dropout regulator and the extv cc switch. the driver and control circuits are powered from this voltage source.must be decoupled to power ground with a minimum of 4.7 f tantalum or other low esr capacitor.extv cc (pin 22/pin 21): external power input to an internal switch connected to intv cc . this switch closes and supplies v cc power, bypassing the internal low drop- out regulator, whenever extv cc is higher than 7.3v. see extv cc connection in applications section. do not exceed 8.5v on this pin.bg1, bg2 (pins 23, 19/pins 22, 18): high current gate drives for bottom (synchronous) n-channel mosfets.voltage swing at these pins is from ground to intv cc . v in (pin 24/pin 23): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin.boost1, boost2 (pins 25, 18/pins 24, 17): bootstrapped supplies to the top side floating drivers. capacitors areconnected between the boost and switch pins and schot- tky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). sw1, sw2 (pins 26, 17/pins 25, 15): switch node connections to inductors. voltage swing at these pins isfrom a schottky diode (external) voltage drop below ground to v in . tg1, tg2 (pins 27, 16/pins 26, 14): high current gate drives for top n-channel mosfets. these are the outputsof floating drivers with a voltage swing equal to intv cc 0.5v superimposed on the switch node voltage sw.pgood (pin 28/pin 27): open-drain logic output. pgood is pulled to ground when the voltage on either v osense pin is not within 7.5% of its set point. exposed pad (pin 33, uh package): signal ground. must be soldered to the pcb ground for electrical contact andoptimum thermal performance. g package/uh package downloaded from: http:/// 9 ltc3727lx-1 3727lx1fa figure 2 fu ctio al diagra u u w (refer to functional diagram) operatio u main control loopthe ltc3727lx-1 uses a constant-frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i1, resets the rs latch. the peak inductor current at which i1 resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error amplifier ea. the v osense pin receives switch logic + 0.8v 7.3v 7.5v v in v in 7v binh clk2 clk1 0.18 a r6r5 + fcb + + + + v ref internal supply 3.3v out v sec r lp c lp 1.5v fcb extv cc intv cc sgnd + 7.5v ldoreg sw shdn 0.55v top boost tg c b c in d 1 d b pgnd bot bg intv cc intv cc v in + c sec c out v out 3727lx1 f02 d sec r sense r2 + v osense drop out det run soft start bot top on sr qq oscillator phase det pllfltr pllin fcb ea 0.86v 0.80v ov v fb 1.2 a 6v r1 + r c 4(v fb ) rst shdn run/ss i th c c c c2 c ss + 4(v fb ) 0.86v slope comp 3mv + + sense sense + intv cc 50k 25k 2.4v 25k 50k i1 i2 b duplicate for secondcontroller channel + + 100k f in + + + + pgood v osense1 v osense2 0.86v0.74v 0.86v 0.74v the voltage feedback signal, which is compared to theinternal reference voltage by the ea. when the load current increases, it causes a slight decrease in v osense relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches thenew load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current compara- tor i2, or the beginning of the next cycle. downloaded from: http:/// 10 ltc3727lx-1 3727lx1fa (refer to functional diagram) the top mosfet drivers are biased from floating boot-strap capacitor c b , which normally is recharged during each off cycle through an external diode when the topmosfet turns off. as v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector de-tects this and forces the top mosfet off for about 400ns every tenth cycle to allow c b to recharge. the main control loop is shut down by pulling the run/sspin low. releasing run/ss allows an internal 1.2 a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, the i th pin voltage is gradually released allowing normal, full-current opera-tion. when both run/ss1 and run/ss2 are low, all ltc3727lx-1 controller functions are shut down, includ- ing the 7.5v and 3.3v regulators. low current operation the fcb pin is a multifunction pin providing two func-tions: 1) to provide regulation for a secondary winding by temporarily forcing continuous pwm operation on both controllers; and 2) to select between two modes of low current operation. when the fcb pin voltage is below0.8v, the controller forces continuous pwm current mode operation. in this mode, the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v intvcc 1v but greater than 0.8v, the controller enters burst mode operation. burstmode operation sets a minimum output current level before inhibiting the top switch and turns off the synchro- nous mosfet(s) when the inductor current goes nega- tive. this combination of requirements will, at low cur- rents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of both output mosfets untilthe output voltage drops. there is 60mv of hysteresis in the burst comparator b tied to the i th pin. this hysteresis produces output signals to the mosfets that turn themon for several cycles, followed by a variable ?leep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by operatio u having the hysteretic comparator follow the error ampli-fier gain block. frequency synchronization the phase-locked loop allows the internal oscillator to besynchronized to an external source via the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator that operates over a 250khz to 550khz range corresponding to a dc voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when pllin is left open, the pllfltr pin goes low, forcing the oscillator to its mini- mum frequency. continuous current (pwm) operationtying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boost- ing the input supply. intv cc /extv cc power power for the top and bottom mosfet drivers and mostother internal circuitry is derived from the intv cc pin. when the extv cc pin is left open, an internal 7.5v low dropout linear regulator supplies intv cc power. if extv cc is taken above 7.3v, the 7.5v regulator is turned off and aninternal switch is turned on connecting extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regu-lator itself or a secondary winding, as described in the applications information section. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. downloaded from: http:/// 11 ltc3727lx-1 3727lx1fa power good (pgood) pinthe pgood pin is connected to an open drain of an internal mosfet. the mosfet turns on and pulls the pin low when either output is not within 7.5% of the nominal output level as determined by the resistivefeedback divider. when both outputs meet the 7.5% requirement, the mosfet is turned off within 10 s and the pin is allowed to be pulled up by an external resistorto a source of up to 7v. theory and benefits of 2-phase operation the ltc3727lx-1 dual high efficiency dc/dc controller brings the considerable benefits of 2-phase operation to portable applications. notebook computers, pdas, hand- held terminals and automotive electronics will all benefit from the lower input filtering requirement, reduced elec- tromagnetic interference (emi) and increased efficiency associated with 2-phase operation. when constant-frequency dual switching regulators oper- ate both channels in phase (i.e., single-phase operation), both switches turn on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasingboth emi and losses in the input capacitor and battery. with 2-phase operation, the two channels of the dual-switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a significant reduc- tion in total rms input current, which in turn allows less expen sive input capacitors to be used, reduces shielding requirements for emi and improves real world operating efficiency. figure 3 compares the input waveforms for a representa-tive single-phase dual switching regulator to the new ltc3727lx-1 2-phase dual switching regulator. an actual measurement of the rms input current under these con- ditions shows that 2-phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduction in itself, remember that the powerlosses are proportional to i rms 2 , meaning that the actual power wasted is reduced by a factor of 2.66. the reducedinput ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. im- provements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. (refer to functional diagram) operatio u (b) (a) 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div i in(meas) = 1.55a rms 3727lx1 f03b i in(meas) = 2.53a rms 3727lx1 f03a figure 3. input waveforms comparing single-phase (a) and 2-phase (b) operation fordual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the ltc3727lx-1 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves efficiency downloaded from: http:/// 12 ltc3727lx-1 3727lx1fa figure 1 on the first page is a basic ltc3727lx-1application circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets and d1 are selected. finally, c in and c out are selected. the circuit shown in figure 1 can be configured foroperation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the ltc3727lx-1 current comparator has a maximumthreshold of 135mv/r sense and an input common mode range of sgnd to 14v. the current comparator thresholdsets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, ? i l . allowing a margin for variations in the ltc3727lx-1 andexternal component values yields: r mv i sense max = 90 when using the controller in very low dropout conditions,the maximum output current level will be reduced due to the internal compensation required to meet stability crite-rion for buck regulators operating at greater than 50% duty factor. a curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. operating frequency the ltc3727lx-1 uses a constant-frequency phase-lock- able architecture with the frequency determined by an internal capacitor. this capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to phase- locked loop and frequency synchronization in the appli- cations information section for additional information. a graph for the voltage applied to the pllfltr pin vs frequency is given in figure 5. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 550khz. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. however, a applicatio s i for atio wu uu (refer to functional diagram) operatio u figure 4. rms input current comparison input voltage (v) 0 input rms current (a) 3.02.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3727lx1 f04 single phasedual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a of course, the improvement afforded by 2-phase opera-tion is a function of the dual switching regulator? relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 4 shows how the rms input current varies for single-phase and 2-phaseoperation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. downloaded from: http:/// 13 ltc3727lx-1 3727lx1fa figure 5. pllfltr pin voltage vs frequency operating frequency (khz) 200 250 300 350 550 400 450 500 pllfltr pin voltage (v) 3727lx1 f05 2.52.0 1.5 1.0 0.5 0 higher frequency generally results in lower efficiencybecause of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ? i l decreases with higher induc- tance or frequency and increases with higher v in : ? i fl v v v l out out in = ? ? ? ? ? ? 1 1 ()( ) accepting larger values of ? i l allows the use of low inductances, but results in higher output voltage rippleand greater core losses. a reasonable starting point for setting ripple current is ? i l = 0.3(i max ). the maximum ? i l occurs at the maximum input voltage.the inductor value also has secondary effects. the transi- tion to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher ? i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency inthe upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the inductance value is determined, the type ofinductor must be selected. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance in- creases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper (i 2 r) losses will increase. ferrite designs have very low core loss and are preferredat high switching frequencies, so designers can concen- trate on reducing i 2 r loss and preventing saturation. ferrite core material saturates ?ard,?which means thatinductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and don? radiate much energy, but gener- ally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. new designs for high current surface mount inductors are available from numerous manufacturers, including coiltronics, vishay, tdk, pulse, panasonic, wuerth, coilcraft, tokoand sumida. power mosfet and d1 selection two external power mosfets must be selected for each controller in the ltc3727lx-1: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 7.5v during start-up (seeextv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications.the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the downloaded from: http:/// 14 ltc3727lx-1 3727lx1fa bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less.selection criteria for the power mosfets include the on-resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when theltc3727lx-1 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v out in = synchronous switchduty cycle vv v in out in = the mosfet power dissipations at maximum outputcurrent are given by: p v v ir kv i main out in max ds on in ma = () + () + () 2 2 1 () x xr s s cf () ( ) ( ) p vv v ir sync in out in max ds on = () + () () 2 1 where is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current.both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses,which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with largermosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high inputvoltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mos- fet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the mainswitch dissipation equation. the schottky diode d1 shown in figure 2 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead- time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regionsof operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. schottky diodes should be placed in parallel with the synchronous mosfets when operating in pulse-skip mode or in burst mode operation. c in and c out selection the selection of c in is simplified by the multiphase archi- tecture and its impact on the worst-case rms currentdrawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms currentrequirement. increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input rms ripple current from this maximum value (see figure 4). the out-of-phase technique typically re- duces the input capacitor? rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. the type of input capacitor, value and esr rating have efficiency effects that need to be considered in the selec- tion process. the capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 22 f to 47 f is usually sufficient for a 25w output supply operating at 250khz. the esr ofthe capacitor is important for capacitor power dissipation as well as overall battery efficiency. all of the power (rms ripple current ?esr) not only heats up the capacitor but wastes power from the battery. medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage applicatio s i for atio wu uu downloaded from: http:/// 15 ltc3727lx-1 3727lx1fa coefficients are very high and may have audible piezoelec-tric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics?higher esr and dryout possibility require several to be used. multiphase systems allow the lowest amount of capacitance overall. as little as one 22 f or two to three 10 f ceramic capaci- tors are an ideal choice in a 20w to 35w power supply dueto their extremely low esr. even though the capacitance at 20v is substantially below their rating at zero-bias, very low esr loss makes ceramics an ideal candidate for highest efficiency battery operated systems. also con- sider parallel ceramic and high quality electrolytic capaci- tors as an effective means of achieving esr and bulk capacitance goals. in continuous mode, the source current of the top n-chan- nel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitorsized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c quiredi i vvv v in rms max out in out i re / ? ? () ? ? ? ? 12 nn this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviationsdo not offer much relief. note that capacitor manufacturer? ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the benefit of the ltc3727lx-1 multiphase can be calcu- lated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switch on at the same time. the total rms power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitor? esr. this is why the input capacitor? requirement calculated above for the worst-case controller is adequate for the dual controllerdesign. remember that input protection fuse resistance, battery resistance and pc board trace resistance losses are also reduced due to the reduced peak currents in a multiphase system. the overall benefit of a multiphase design will only be fully realized when the source imped- ance of the power supply/battery is included in the effi- ciency testing. the drains of the two top mosfets should be placed within 1cm of each other and share a commonc in (s). separating the drains and c in may produce unde- sirable voltage and current resonances at v in . the selection of c out is driven by the required effective series resistance (esr). typically once the esr require-ment is satisfied the capacitance is adequate for filtering. the output ripple ( ? v out ) is determined by: ?? vi e s r fc out l out ? + ? ? ? ? ? ? 1 8 where f = operating frequency, c out = output capaci- tance, and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. with ? i l = 0.3i out(max) the output ripple will typically be less than 50mv at max v in assuming: c out recommended esr < 2 r sense and c out > 1/(8fr sense ) the first condition relates to the ripple current into theesr of the output capacitance while the second term guarantees that the output capacitance does not signifi- cantly discharge during the operating frequency period due to ripple current. the choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation components can be optimized to provide stable, highperformance transient response regardless of the output capacitors selected. manufacturers such as nichicon, nippon chemi-con andsanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric applicatio s i for atio wu uu downloaded from: http:/// 16 ltc3727lx-1 3727lx1fa capacitor available from sanyo has the lowest (esr)(size)product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications multiple capacitors may need to be used in parallel to meet the esr, rms current handling and load step requirements of the application. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. spe- cial polymer surface mount capacitors offer very low esr but have lower storage capacity per unit volume than other capacitor types. these capacitors offer a very cost-effec- tive output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tps series iii or the kemet t510 series of surface mount tantalums, available in case heights ranging from 1.2mm to 4.1mm. aluminum electrolytic capacitors can be used in cost- driven applications providing that consideration is given to ripple current ratings, temperature and long term reliability. a typical application will require several to many aluminum electrolytic capacitors in parallel. a combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. other capacitor types include nichicon pl series, nec neocap, cornell dubilier esre and sprague 595d series. consult manufacturers for other specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces7.5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within theltc3727lx-1. the intv cc pin regulator can supply a peak current of 50ma and must be bypassed to groundwith a minimum of 4.7 f tantalum, 10 f special polymer, or low esr type electrolytic capacitor. a 1 f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing isnecessary to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between channels. higher input voltage applications in which large mosfetsare being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3727lx-1 to be exceeded. the system supply current is normally dominated by the gate charge current. additional external loading of the intv cc and 3.3v linear regulators also needs to be taken into account for the power dissipationcalculations. the total intv cc current can be supplied by either the 7.5v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 7.3v, all of the intv cc current is supplied by the internal 7.5v linear regulator. power dissipation for the icin this case is highest: (v in )(i intvcc ), and overall efficiency is lowered. the gate charge current is dependent onoperating frequency as discussed in the efficiency consid- erations section. the junction temperature can be esti- mated by using the equations given in note 2 of the electrical characteristics. for example, the ltc3727lx-1 v in current is limited to less than 24ma from a 24v supply when not using the extv cc pin as follows: t j = 70 c + (24ma)(24v)(95 c/w) = 125 c use of the extv cc input pin reduces the junction tempera- ture to: t j = 70 c + (24ma)(7.5v)(95 c/w) = 87 c dissipation should be calculated to also include any addedcurrent drawn from the internal 3.3v linear regulator. to prevent maximum junction temperature from being ex- ceeded, the input supply current must be checked operat- ing in continuous mode at maximum v in . extv cc connection the ltc3727lx-1 contains an internal p-channel mos-fet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 7.3v, the internal regulator is turned off and the switchcloses, connecting the extv cc pin to the intv cc pin thereby supplying internal power. the switch remainsclosed as long as the voltage applied to extv cc remains above 7.0v. this allows the mosfet driver and control power to be derived from the output during normal opera- applicatio s i for atio wu uu downloaded from: http:/// 17 ltc3727lx-1 3727lx1fa tion (7.2v < v out < 8.5v) and from the internal regulator when the output is out of regulation (start-up, short-circuit). if more current is required through the extv cc switch than is specified, an external schottky diode can beadded between the extv cc and intv cc pins. do not apply greater than 8.5v to the extv cc pin and ensure that extv cc 19 ltc3727lx-1 3727lx1fa circuit ripple current is determined by the minimum on-time t on(min) of the ltc3727lx-1 (less than 200ns), the input voltage and inductor value: ? i l(sc) = t on(min) (v in /l) the resulting short-circuit current is: i mv r i sc sense lsc =+ 45 1 2 ? () fault conditions: overvoltage protection (crowbar)the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage condi- tions. the comparator (ov) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvolt- age condition is cleared. the output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor pc layout to function while the design is being debugged. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted topmosfet will result in a high current condition which will open the system fuse. the switching regulator will regu- late properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. phase-locked loop and frequency synchronization the ltc3727lx-1 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detec- tor. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage applied to the pllfltr pin of 1.2v corresponds to a frequency of approximately380khz. the nominal operating frequency range of the ltc3727lx-1 is 250khz to 550khz. the phase detector used is an edge sensitive digital typewhich provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range, ? f h , is equal to the capture range, ? f c: ? f h = ? f c = 0.5 f o (250khz-550khz) the output of the phase detector is a complementary pairof current sources charging or discharging the external filter network on the pllfltr pin. if the external frequency (f pllin ) is greater than the oscil- lator frequency f 0sc , current is sourced continuously, pulling up the pllfltr pin. when the external frequencyis less than f 0sc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal fre-quencies are the same but exhibit a phase difference, the current sources turn on for an amount of time correspond- ing to the phase difference. thus the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the ltc3727lx-1 pllin pin must be driven from a lowimpedance source such as a logic gate located close to the pin. when using multiple ltc3727lx-1s for a phase- locked system, the pllfltr pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master? frequency. a dc voltage of 0.7v to 1.7v applied to the master oscillator? pllfltr pin is recommended in order to meet this requirement. the resultant operating frequency can range from 310khz to 470khz. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable inputto the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k ? and c lp is 0.01 f to 0.1 f. minimum on-time considerationsminimum on-time t on(min) is the smallest time duration that the ltc3727lx-1 is capable of turning on the topmosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty applicatio s i for atio wu uu downloaded from: http:/// 20 ltc3727lx-1 3727lx1fa cycle applications may approach this minimum on-timelimit and care should be taken to ensure that t v vf on min out in () () < if the duty cycle falls below what can be accommodated bythe minimum on-time, the ltc3727lx-1 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3727lx-1 is generally less than 200ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skip- ping can occur with correspondingly larger inductor cur- rent and output voltage ripple. fcb pin operation the fcb pin can be used to regulate a secondary winding or as a logic level input. continuous operation is forced on both controllers when the fcb pin drops below 0.8v. during continuous mode, current flows continuously in the transformer primary. the secondary winding(s) draw current only when the bottom, synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for asufficient amount of time to transfer power from the output capacitor to the secondary load. forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in figure 6 by the turns ratio n of the transformer: v sec ? (n + 1) v out however, if the controller goes into burst mode operationand halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : vv r r sec min () . ? + ? ? ? ? ? ? 08 1 6 5 where r5 and r6 are shown in figure 2.if v sec drops below this level, the fcb voltage forces temporary continuous switching operation until v sec is again above its minimum.in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.18 a internal current source pulling the pin high. include thiscurrent when choosing resistor values r5 and r6. the following table summarizes the possible states avail- able on the fcb pin: table 2 fcb pin condition 0v to 0.75v forced continuous both controllers (current reversal allowed burst inhibited) 0.85v < v fcb < 6.0v minimum peak current induces burst mode operationno current reversal allowed feedback resistors regulating a secondary winding >7.3v burst mode operation disabled constant frequency mode enabledno current reversal allowed no minimum peak current voltage positioningvoltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. the open-loop dc gain of the control loop is reduced depending upon the maximum load step specifications. voltage positioning can easily be added to the ltc3727lx-1 by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equalto the midpoint operating voltage range of the error amplifier, or 1.2v (see figure 8). the resistive load reduces the dc loop gain while main- taining the linear control range of the error amplifier. the maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a applicatio s i for atio wu uu downloaded from: http:/// 21 ltc3727lx-1 3727lx1fa complete explanation is included in design solutions 10(see www.linear.com). supplying intv cc power through the extv cc switch input from an output-derived source will scale the v in current required for the driver and control circuits by afactor of (duty cycle)/(efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver waspowered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis-tor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is ?hopped?between the topside mosfet and the synchronous mosfet. if the two mosfetshave approximately the same r ds(on) , then the resis- tance of one mosfet can simply be summed with theresistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m ? , r l = 50m ? , r sense = 10m ? and r esr = 40m ? (sum of both input and output capacitance losses), then the total resis-tance is 130m ? . this results in losses ranging from 3% to 13% as the output current increases from 1a to 5afor a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. thecombined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at highinput voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other ?idden?losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these ?ystem?level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25w supply will typically require a mini- applicatio s i for atio wu uu figure 8. active voltage positioning applied to the ltc3727lx-1 i th r c r t1 intv cc c c 3727lx1 f08 ltc3727lx-1 r t2 efficiency considerationsthe percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% ?(l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentageof input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3727lx-1 circuits: 1) ltc3727lx-1 v in current (including loading on the 3.3v internal regulator),2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses.1. the v in current has two components: the first is the dc supply current given in the electrical characteristicstable, which excludes mosfet driver and control cur- rents; the second is the current drawn from the 3.3v linear regulator output. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current resultsfrom switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg =f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. downloaded from: http:/// 22 ltc3727lx-1 3727lx1fa the feedback loop. placing a power mosfet directlyacross the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated controlloop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in themost critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallelwith c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent thissudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited toapproximately 25 ?c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma.automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a naturalinterest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during opera- tion. but before you connect, be advised: you are plugging into the supply from hell. the main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. load-dump is the result of a loose battery cable. when thecable breaks connection, the field collapse in the alternator mum of 22 f to 47 f of capacitance having a maximum of 20m ? to 50m ? of esr. the ltc3727lx-1 2-phase architecture typically halves this input capacitance re-quirement over competing solutions. other losses, in- cluding schottky diode conduction losses during dead- time and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change andreturn v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response . assuming a pre- dominantly second order system, phase margin and/ordamping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit willprovide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly(from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking applicatio s i for atio wu uu downloaded from: http:/// 23 ltc3727lx-1 3727lx1fa the r sense resistor value can be calculated by using the maximum current sense voltage specification with someaccommodation for tolerances: r mv a sense ?? 90 6 0 015 . choosing 1% resistors; r1 = 20k and r2 = 280k yields anoutput voltage of 12v. the power dissipation on the top side mosfet can be easily estimated. choosing a siliconix si4412dy results in: r ds(on) = 0.042 ? , c rss = 100pf. at maximum input voltage with t(estimated) = 50 c: p v v cc main = () + [] 1230 5 1 0 005 50 25 0 042 2 (. )( ) . ?? () + () () ( ) ( ) = 1 7 30 5 100 250 664 2 .va p f k h z mw a short-circuit to ground will result in a folded backcurrent of: i mv ns v h a sc = ? + ? ? ? ? ? ? = 45 0 015 1 2 200 30 14 32 . () . with a typical value of r ds(on) and = (0.005/ c)(20) = 0.1. the resulting power dissipated in the bottommosfet is: p vv v a mw sync = () () ? () = 30 12 30 32 11 0042 284 2 ... which is less than under full-load conditions.c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 ? for low output ripple. the output ripple in continuous mode will be highest at themaximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( ? i l ) = 0.02 ? (2a) = 40mv p? can cause a positive spike as high as 60v which takesseveral hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 9 is the most straight forward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc3727lx-1 has a maximum input voltage of 32v, most applications will be limited to 30v by the mosfet bvdss. applicatio s i for atio wu uu figure 9. automotive application protection v in 3727lx1 f09 ltc3727lx-1 transient voltagesuppressor general instrument 1.5ka24a 50a i pk rating 12v design exampleas a design example for one channel, assume v in = 24v(nominal), v in = 30v(max), v out = 12v, i max = 5a and f = 250khz.the inductance value is chosen first based on a 40% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the pllfltr pin to the sgnd pin for 250khz operation. the minimum inductance for 40% ripple current is: ? i v fl v v l out out in = ? ? ? ? ? ? ()( ) 1 a 14 h inductor will result in 40% ripple current. the peak inductor current will be the maximum dc value plus onehalf the ripple current, or 6a, for the 14 h value. downloaded from: http:/// 24 ltc3727lx-1 3727lx1fa pc board layout checklistwhen laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3727lx-1. these items are also illustrated graphically in the layout diagram of figure 10; figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in continuous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1cm of each other with a common drain connec-tion at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ltc3727lx-1 signal ground pin and theground return of c intvcc must return to the combined c out (? terminals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (? terminals should be connected as close aspossible to the (? terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3727lx-1 v osense pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal ofc out and signal ground. the r2 and r4 connections should not be along the high current input feeds fromthe input capacitor(s). 4. are the sense and sense + leads routed together with minimum pc trace spacing? the filter capacitor be-tween sense + and sense should be as close as possible to the ic. ensure accurate current sensing withkelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current applicatio s i for atio wu uu figure 10. ltc3727lx-1 recommended printed circuit layout diagram c b2 c b1 r pu pgood v pull-up (<7v) c intvcc 12 3 4 5 6 7 8 9 1011 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 + c in d1 m1 m2 m3 m4 d2 + c vin v in r in intv cc 3.3v r4 r3 r2 r1 run/ss1sense1 + sense1 v osense1 pllfltrpllin fcb i th1 sgnd3.3v out i th2 v osense2 sense2 sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 ltc3727lx-1 l1 l2 c out1 v out1 gndv out2 3727lx1 f10 + c out2 + r sense r sense f in downloaded from: http:/// 25 ltc3727lx-1 3727lx1fa peaks. an additional 1 f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) awayfrom sensitive small-signal nodes, especially from the opposites channel? voltage and current sensing feed- back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the ?utput side?of the ltc3727lx-1 and occupy mini- mum pc trace area. 7. use a modified ?tar ground?technique: a low imped- ance, large copper area central grounding point on thesame side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feed-back resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller on at a time. it is helpful to usea dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the appli cation. the frequency of operation should be main- tained over the input voltage range down to dropout anduntil the output load drops below the low current opera- tion threshold?ypically 10% to 20% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb imple- mentation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage applicatio s i for atio wu uu figure 11. branch current waveforms r l1 d1 l1 sw1 r sense1 v out1 c out1 + v in c in r in + r l2 d2 bold lines indicatehigh switching current. keep lines to a minimum length l2 sw2 3727lx1 f11 r sense2 v out2 c out2 + downloaded from: http:/// 26 ltc3727lx-1 3727lx1fa applicatio s i for atio wu uu sensing inputs or inadequate loop compensation. over-compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current com- parator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the under-voltage lockout circuit by further lowering v in while moni- toring the outputs to verify operation.investigate whether any problems exist only at higher output currents or only at higher input voltages. if prob- lems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across thecurrent sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are en- countered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive currentand voltage sensing traces. in addition, investigate com- mon ground path voltage pickup between these compo- nents and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistor?on? worry, the regulator will still maintain control of the output voltage. 0.1 f 4.7 f 12 3 4 5 6 7 8 9 1011 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 + 22 f 50v d1mbrm 140t3 d2 mbrm 140t3 m1a m1b m2a m2b 1 f 10v 0.1 f 10 ? 0.015 ? 0.015 ? f sync 3.3v 0.1 f 10k 105k 1% 33pf 15k 33pf 15k 220pf 220pf 0.01 f 1000pf 1000pf 1000pf 0.1 f 20k 1% 280k 1% 20k 1% run/ss1sense1 + sense1 v osense1 pllfltrpllin fcb i th1 sgnd3.3v out i th2 v osense2 sense2 sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 ltc3727lx-1 l1 8 h l2 15 h c out1 47 f 6.3v c out2 100 f 16v gndv out2 12v4a; 5a peak v out1 5v5a; 6a peak v in 15v to28v 3727lx1 f12 + + v in : 15v to 28v v out : 5v, 5a/12v, 4a switching frequency = 250khzmi, m2: fairchild fds6680a l1: 8 h sumida cdep134-8r0 l2: 15 h coiltronics up4b-150 27pf 27pf 0.1 f cmdsh-3 cmdsh-3 pgood v pull-up (<7v) c out1 : panasonic eefcdoj470r c out2 : sanyo os-con 16svp100m figure 12. ltc3727lx-1 12v/4a, 5v/5a regulator with external frequency synchronization downloaded from: http:/// 27 ltc3727lx-1 3727lx1fa u package descriptio g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) 5.00 0.10 (4 sides) note:1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 31 12 32 bottom view?xposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ?0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 packageoutline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typor 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 g28 ssop 0204 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 1413 9.90 ?10.50* (.390 ?.413) 2526 22 21 20 19 18 17 16 15 2324 2728 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12 downloaded from: http:/// 28 ltc3727lx-1 3727lx1fa part number description comments ltc1625/ltc1775 no r sense tm current mode synchronous step-down controllers 97% efficiency, no sense resistor, 16-pin ssop ltc1702 no r sense 2-phase dual synchronous step-down controller 550khz, no sense resistor ltc1703 no r sense 2-phase dual synchronous step-down controller mobile pentium iii processors, 550khz, v in 7v with 5-bit mobile vid control ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood lt1709/ high efficiency, 2-phase synchronous step-down switching 1.3v v out 3.5v, current mode ensures accurate lt1709-8 regulators with 5-bit vid current sharing, 3.5v v in 36v ltc1735 high efficiency synchronous step-down switching regulator output fault protection, 16-pin ssop ltc1736 h igh efficiency synchronous controller with 5-bit mobile vid control o utput fault protection, 24-pin ssop, 3.5v v in 36v ltc1876 triple output dc/dc synchronous controller dual, 2-phase step-down and step-up dc/dc converter, 2.6v v in 36v, fixed frequency 150khz to 300khz ltc1778 no r sense wide input range synchronous step-down controller up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc1929/ 2-phase synchronous controllers up to 42a, uses all surface mount components, ltc1929-pg no heat sinks, 3.5v v in 36v ltc3727/ltc3727-1/ dual, 2-phase synchronous controllers very low dropout; v out 14v, 4v v in 36v ltc3727a-1 ltc3728 2-phase 550khz, dual synchronous step-down controller qfn and ssop packages, high frequency for smaller l and c ltc3729 20a to 200a polyphase synchronous controllers expandable from 2-phase to 12-phase, uses all surface mount components, no heat sink ltc3731 3-phase, 600khz synchronous step-down controller 0.6v v out 6v, 4.5v v in 32v, i out 60a, integrated mosfet drivers ltc3827/ltc3827-1 low i q , dual 2-p hase synchronous controllers 80 a quiescent current 4v v in 36v, 0.8v v out 10v polyphase is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0107 printed in usa related parts figure 13. ltc3727lx-1 8.5v/3a, 5v/5a regulator 0.1 f 4.7 f + 22 f 50v d1mbrm 140t3 d2 mbrm 140t3 m1a m1b m2a m2b 1 f 10v 0.1 f 10 ? 0.015 ? 0.015 ? 3.3v 0.1 f 105k 1% 33pf 15k 33pf 15k 220pf 220pf 1000pf 1000pf 0.1 f 20k 1% 192.5k, 1% 20k 1% sense2 + 3.3v out v osense2 i th2 sense2 sgnd i th1 fcb pllin pllfltr v osense1 sense1 sense1 + run/ss1 run/ss2 bg2 sw2 boost2 tg2 pgnd intv cc extv cc bg1 v in boost1 sw1 tg1 pgood 2118 16 1715 19 20 22 23 24 25 26 27 28 ltc3727lx-1 l1 8 h l2 8 h c out1 47 f, 6.3v c out2 100 f 16v gnd v out2 8.5v3a; 4a peak v out1 5v5a; 6a peak v in 10v to 15v 3727lx1 f13 + + 27pf 27pf 0.1 f cmdsh-3 cmdsh-3 pgood v pull-up (<7v) c out1 : panasonic eefcdoj470r c out2 : sanyo os-con 16svp100m v in : 10v to 15v v out : 5v, 5a/8.5v, 3a switching frequency = 250khzmi, m2: fairchild fds6680a l1, l2: 8 h sumida cdep134-8r0 14 1012 1113 9 8 7 6 5 4 3 2 1 u typical applicatio downloaded from: http:/// |
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